1. Field of the Invention
The present invention relates to redundancy repair of a semiconductor memory device. More particularly, it relates to the rapid identification and efficient repair of defective memory cells.
2. Description of the Related Art
Large-scale integrated semiconductor memory devices generally have redundant rows or columns of memory cells that can be used to replace defective rows or columns if the defect is found before the device is packaged. Defects can be found by writing known data into all memory cells, then reading the data, but this type of test takes considerable time. A faster way to test the memory device is to write known data into all memory cells, then compare the data in pairs of memory cells and read the comparison results, thereby reducing the read-out time by half.
A conventional semiconductor memory device employing this type of comparison test includes a plurality of memory cell arrays. After identical data have been written into all of the memory cell arrays, two of the memory cell arrays are selected and data from corresponding memory cells in the two arrays are read simultaneously onto complementary pairs of data bus lines. If the data match, then in each pair of data bus lines, one line will go high and the other line will go low, whereas non-matching data will cause both lines to go to the same logic level, e.g., both to the low level. In the comparison test output mode, the input-output buffer connected to the complementary pair of data bus lines functions as, for example, an OR gate, producing high output in the normal (matching) case and low output in the defective (non-matching) case.
A problem with this scheme is that when a defective bit is detected, it is not known which of the two memory cells being compared is defective. Since these two memory cells are located in different memory cell arrays, it is not known which memory cell array should be repaired. Accordingly, after a defective bit has been detected, a further test is needed to isolate the defect to a particular memory cell array.
If the memory device has redundant columns and each redundant column spans all the memory cell arrays, a conventional arrangement that has often been used in the past, the above problem becomes irrelevant, since both of the compared memory cells are replaced. This conventional arrangement unduly limits the number of defects that can be repaired, however. If a defect in a particular column is limited to a particular memory cell array, it is obviously inefficient to replace the same column in other, non-defective memory cell arrays.
It would be desirable if a defect could be detected and isolated to a single memory cell array in a single step, and if the defect could be repaired by replacing memory cells only in the defective memory cell array.